Showing posts with label bit. Show all posts
Showing posts with label bit. Show all posts

Half Adder and Full Adder : Logic Design Lab Experiments

Aim:
1. To design and set up a half adder using

  • (a) XOR gates and NAND gates
  • (b) NAND gates only

2. To clesign and set up a full adder using

  • (a) XOR gates and NAND gates
  • (b) NAND gates only