Half Adder and Full Adder : Logic Design Lab Experiments

Aim:
1. To design and set up a half adder using

• (a) XOR gates and NAND gates
• (b) NAND gates only

2. To clesign and set up a full adder using

• (a) XOR gates and NAND gates
• (b) NAND gates only

Components and equipments required:

ICs 7400, 7486 and IC trainer kit.

Theory:

The simplest binary adder is called a half adder. Half adder has two input bits and two output bits, One output bit is the sum and the other is carry. They are represented by S and C respectively in the logic symbol.


A half adder has no provision to add a carry from the lower order bits when binary numbers are added. When two input bits and a carry are to be added, the number of input bits become three and the input combinations increases to eight. For this, a full adder is used. Like half adder, it also has a sum bit and a carry bit. The new carry generated is represented by C_n and carry generated from the previous addition is represented by C_n-1.

Half Adder:

Half adder Logical circuit design and truth table

Full Adder:

Procedure

1. Verify whether all the components and wires are in good condition.
2. Set up the half adder circuit and feed the input bit combinations.
3. Observe the output corresponding to input combinations and enter it in the truth table.
4. Repeat the above steps for a full adder circuit.