We can construct meaningful derivation trees that enable us to represent arithmetic expressions in infix, prefix and postfix forms. A binary tree is enough to represent all these three notations of arithmetic expressions. Both prefix and postfix notations are unintelligable for humans. But they are of great use in computer science. Compilers often convert infix to prefix notation and then to assembler code. From a derivation tree of an algebraic expression, we can get equivalent prefix and postfix notations. An algebraic expression in terms of operators and operands can be derived by an ambiguous context-free grammar. Prefix notation is the parenthesis-free notational scheme invented by Polish logician Jan Lukasiewicz and is often called polish notation. In prefix notation operators are followed by operands.
For example, in prefix notation A + B is written as +AB. Postfix notation is reverse of prefix notation. AB+ is the equivalent postfix notation of A + B. The infix form is evaluated and the binary tree is created according to the priority of the operators. Let us start from the simplest examples.
Showing posts with label binary. Show all posts
Showing posts with label binary. Show all posts
Binary to Gray Code Converter
This post is to teach you how to convert binary number to corresponding Gray code. The conversion is so simple. You can see it..
If an n bit binary number is represented by Bn Bn-1 ...B1 and its Gray code equivalent by Gn Gn-1...G1 where Bn and Gn are the most significant bits (MSBs), then the Gray code bits are obtained from the binary code as follows. The symbol ⊕ stands for the Exclusive OR (XOR) operation explained below.
The conversion procedure is as follows:
If an n bit binary number is represented by Bn Bn-1 ...B1 and its Gray code equivalent by Gn Gn-1...G1 where Bn and Gn are the most significant bits (MSBs), then the Gray code bits are obtained from the binary code as follows. The symbol ⊕ stands for the Exclusive OR (XOR) operation explained below.
The conversion procedure is as follows:
Half Adder and Full Adder : Logic Design Lab Experiments
Aim:
1. To design and set up a half adder using
2. To clesign and set up a full adder using
1. To design and set up a half adder using
- (a) XOR gates and NAND gates
- (b) NAND gates only
2. To clesign and set up a full adder using
- (a) XOR gates and NAND gates
- (b) NAND gates only
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